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FEDL9225B-03
1 Semiconductor MSM9225B
CAN (Controller Area Network) Controller
This version: Aug. 2001 Previous version: Feb. 2001
GENERAL DESCRIPTION
The MSM9225B is a microcontroller peripheral LSI which conforms to the CAN protocol for high-speed LANs in automobiles.
FEATURES
* Conforms to CAN protocol specification (Bosch, V2.0 part B/Active) * Maximum of 1 Mbps bit rate * Communication method: * Transmission line is bi-directional, two-wire serial communication * NRZ (Non-Return to Zero) system using bit stuff function * Multi-master system * Broadcast system * Message boxes: * Up to 16 message boxes can be used, and messages up to 8 bytes long can be transmitted or received for each message box. * Number of received messages can be extended by group message function (up to 2 groups can be set) * Overwrite flag is provided * Priority control by identifier * 2032 types in standard format, 2032 x 218 types in extended format * Microcontroller interface * Corresponding to both parallel and serial interface Parallel interface: Separate address/data bus type (with address latch signal/no address latch signal) and multiplexed address/data bus type Serial interface: Synchronous communication type * Three interrupt sources: Transmission/receive/error * Error control: * Bit error/stuff error/CRC error/form error/acknowledgment error detection functions * Retransmission/error status monitoring function when error occurs * Bit error flag/stuff error flag/CRC error flag/form error flag/acknowledge error flag are provided * Communication control by remote data request function * Sleep/Stop mode function * Supply voltage: 5 V10% * Operating temperature: -40 to +125C * Package: 44-pin plastic QFP (QFP44-P-910-0.80-2K) (Product name: MSM9225BGA-2K)
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BLOCK DIAGRAM
CS A7-0 AD7-0/D7-0 PALE PWR PRD/SRW PRDY/SWAIT 8 8
Parallel I/F
Bit timing logic (BTL) microcontroller interface
Bit stream logic (BSL)
RD RDY RW WAIT
Transmission control logic (TCL) Message memory Control register Data management logic
Tx0 Tx1
SCLK SDI SDO INT Mode1, 0 XT XT RESET
Serial I/F
Error management logic (EML)
Timing generator
Receive control logic (RCL)
Rx0 Rx1
VDD GND
CONFIGURATION EXAMPLE
ABS CAN
Engine controller
Power steering
CAN
Seat-position controller
Suspension
CAN CAN CAN Bus
CAN CAN
Transmission
CAN
Automatic air conditioner
CAN CAN
Power window Outside mirror controller
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PIN CONFIGURATION
33 AD2/D2 32 AD1/D1 31 AD0/D0 30 Mode1 25 RESET 24 VDD 29 Mode0 28 GND 27 PALE 26 PWR
AD3/D3 34 AD4/D4 35 AD5/D5 36 AD6/D6 37 AD7/D7 38 GND 39 VDD 40 A0 41 A1 42 A2 43 A3 44 10 1 2 3 4 5 GND 6 SDI 7 8 9 11 INT
23 TX1 22 TX0 21 GND 20 VDD 19 RX1 18 RX0 17 GND 16 PRDY/SWAIT 15 GND 14 XT 13 XT 12 VDD
A7 SDO
A4
A5 A6
SCLK
PRD/SRW
44-Pin Plastic QFP (Top View)
CS
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PIN DESCRIPTIONS
Symbol Pin Type Description Chip select pin. When "L", PALE, PWR, PRD/SRW, SCLK and SDO pins (microcontroller interface pins) are valid. When "H", these pins are invalid. A7-0 41-44, 1-4 I Address bus pins (when using separate buses). If used with a multiplexed bus or if used in the serial mode, fix these pins at "H" or "L" levels. Multiplexed bus: Address/data pins (AD7-0) Separate buses: Data pins (D7-0) If used in the serial mode, fix these pins at a "L" levels. Write input pin if used in the parallel mode. Data is captured when this pin is at a "L" level. If used in the serial mode, fix this pin at a "L" level. Parallel mode: Read signal pin (PRD) When at a "L" level, data is output from the data pins. Serial mode: Read/write signal pin (SRW) When at a "H" level, data is output from the SDO pin. When at a "L" level, the SDO pin is at high impedance, and data is captured beginning with the second byte of data input from the SDI pin. Address latch signal pin When at a "H" level, addresses are captured. If used in the parallel mode and the address latch signal is unnecessary or in the serial mode, fix this pin at a "H" or "L" level. Serial data input pin Addresses (1st byte) and data (beginning from the 2nd byte) are input to this pin, LSB first. If used in the parallel mode, fix this pin at a "H" or "L" level. Serial data output pin When the CS pin is at a "H" level, this pin is at high impedance. When CS is at a "L" level, data is output from this pin, LSB first. If used in the parallel mode, fix this pin at a "H" or "L" level. Shift clock input pin for serial data At the rising edge of the shift clock, SDI pin data is captured. falling edge, data is output from the SDO pin. At the
CS
10
I
AD7-0/ D7-0 PWR
31-38
I/O
26
I
PRD/ SRW
9
I
PALE
27
I
SDI
7
I
SDO
5
O
SCLK
8
I
Ready output pin When required by the MSM9225B, a signal may be output to extend the bus cycle until the internal access is completed. PRDY/ SWAIT 16 O Internal access in progress Parallel mode (PRDY) Serial mode (SWAIT) "L" level output "H" level output After completion of access High impedance output "L" level output
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Symbol
Pin
Type
Description Microcontroller interface select pins Mode1 0 0 1 1 Mode0 0 1 0 1 Interface Separate No address latch signal buses With address latch signal Multiplexed buses Serial mode Parallel mode
Mode1, 0
29, 30
I
INT
11
O
Interrupt request output pin When an interrupt request occurs, a "L" level is output. This pin automatically outputs a "H" level after 32 Ts (T = 1/fosc). Three types of interrupts share this pin: transmission complete, reception complete, and error. Reset pin System is reset when this pin is at a "L" level. Clock pins. If internal oscillator is used, connect a crystal (ceramic resonator). If external clock is used, input clock via XT pin. The XT pin should be left open. Receive input pin. Power supply pin GND pin Differential amplifier included. Transmission output pin
RESET XT XT Rx0, Rx1 Tx0, Tx1 VDD GND
25 13 14 18, 19 22, 23 12, 20, 24, 40 6, 15, 17, 21, 28, 39
I I O I O -- --
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ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature Symbol VDD VI VO PD TOP TSTG Condition Ta = 25C -- -- Ta 25C -- -- Rating -0.3 to +7.0 -0.3 to VDD +3.0 -0.3 to VDD +3.0 615 -40 to +125 -65 to +150 Unit V V V mW C C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Symbol VDD TOP Condition VDD = AVDD -- Min. 4.5 -40 Typ. 5.0 +25 Max. 5.5 +125 Unit V C
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ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter "H" Input Voltage "L" Input Voltage "H" Input Current "L" Input Current "H" Output Voltage "L" Output Voltage Output Leakage Current Dynamic Supply Current Static Supply Current Symbol VIH VIL IIH1 IIH2 IIL1 IIL2 VOH1 VOH2 VOL1 VOL2 IIH1 IDD IDDS Applicable pin Applies to all inputs Applies to all inputs XT Other inputs XT Other input INT, PRDY/SWAIT AD7-0/D7-0 INT, PRDY/SWAIT AD7-0/D7-0 PRDY/SWAIT AD7-0/D7-0 -- -- -- (VDD = 4.5 to 5.5 V, Ta = -40 to +125C) Condition Min. Max. Unit -- 0.8VDD VDD +0.3 V -- -0.3 +0.2 VDD V 3 25 A VI = VDD -1.0 +1.0 A -25 -3 A VI = 0V -1.0 +1.0 A -- V VDD -1.0 IOH1 = -80 A -- V VDD -1.0 IOH2 = -400 A IOL1 = 1.6 mA -- 0.4 V IOL2 = 3.2 mA -- 0.4 V VI = VDD/0 V fOSC = 16 MHz, No Load SLEEP Mode STOP Mode -1.0 -- -- -- +1.0 9 400 100 A mA A A
Rx0, Rx1 Characteristics Differencial input mode
(VDD = 4.5 to 5.5 V, Ta = -40 to +125C) Parameter `dominant' Input Voltage `recessive Input Voltage Input Leakage Current Symbol VRx0 (d) VRx0 (r) ILK Applicable pin Rx0 Rx0 Rx0, Rx1 Condition VRx1 = 0.4 VDD to 0.6 VDD VRX1 = VDD/0 V Min. -0.3 VRx1 +0.4 -1 Max. VRx1 -0.4 VDD +3 +1 Unit V V A
Tx0, Tx1 Characteristics
Parameter "H" Output Voltage "L" Output Voltage Symbol VOH VOL Condition IOH = -3.0 mA IOL = 10.0 mA (VDD = 4.5 to 5.5 V, Ta = -40 to +125C) Min. Max. Unit VDD -0.4 -- V -- 0.4 V
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AC Characteristics Parallel mode
Parameter ALE Address Setup Time ALE Address Hold Time PRD Output Data Delay Time PRD Output Data Hold Time ALE "H" Level Width When PRDY is not generated Access Cycle When PRDY is generated Address Hold Time from PRD ALE Delay Time from PRD PRD "H" Level Width PRDY "L" Delay Time PRDY "L" Level Width Data Output Delay Time from PRDY PWR Hold Time from PRDY Input Data Setup Time Input Data Hold Time PRD Delay Time PWR Delay Time Address Hold Time from PWR ALE Delay Time from PWR PWR "H" Level Width PWR "L" Level Width CS Delay Time from PRD CS Delay Time from PWR Symbol tAS tAH tRDLY tRDH tWALEH tcyc tRAH tHRA tWRDH tARLDLY tWRDYL tARDDLY tARWDLY tWDS tWDH tRS tWS tWAH tHWA tWRH tWRL tHRC tHWC (VDD = 4.5 to 5.5 V, Ta = -40 to +125C, fOSC = 16 MHz) Condition Min. Max. Unit -- 10 -- ns -- 10 -- ns 1 -- -- ns 60* -- 5 -- ns -- 16.5 -- ns 4T -- 7T -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 27 27 -- 0 -- 10 30 4 10 10 10 27 40 20*1 0 0 -- -- -- -- 35 2.5T 35 -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns T = 1/fOSC -- ns
The values with *1 indicate those when PRDY is not generated. The values with *1 when PRDY is generated are defined by "Data Output Delay Time from PRDY" tARDDLY and "PWR Hold Time from PRDY" tARWDLY.
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Serial mode
(VDD = 4.5 to 5.5 V, Ta = -40 to +125C, fOSC = 16 MHz) Parameter CS Setup Time CS Hold Time SCLK Cycle SCLK Pulse Width SDI Setup Time SDI Hold Time SDO Output Enable Time SDO Output Disable Time SDO Output Delay Time SRW Setup Time SRW Hold Time SWAIT Output Delay Time SWAIT "H" Level Width Byte Delay Symbol tCS tCH tCP tCW tDS tDH tCSODLY tCSZDLY tPD tRS tRH tSRDLY tWRDY tWAIT Condition -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min. 10 8T 167 83 30 5 -- -- -- 10 0 -- -- 8T Max. -- -- -- -- -- -- 30 30 30 -- -- 2T 6T -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns T = 1/fOSC
Other timing characteristics
(VDD = 4.5 to 5.5 V, Ta = -40 to +125C) Parameter System Clock Cycle RESET "H" Level Input Width RESET "L" Level Input Width INT "L" Level Output Width Symbol tclkcy tWRSTH tWRSTL tWINTL Condition -- -- -- -- Min. 62 5 5 32T Max. -- -- -- -- Unit ns s s ns T = 1/fOSC
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TIMING DIAGRAMS
Separate Bus Mode Read access timing
tHRC CS tcyc A7-0 tRAH AD7-0/ D7-0 tRS PRD/SRW tRDLY tARDDLY tWRDYL PRDY/SWAIT tARLDLY tRDH tWRDH
Note:
The PRDY signal may be output depending on the internal state of the MSM9225B.
Write access timing
tHWC CS tcyc A7-0 tWAH AD7-0/ D7-0 tWS tWRL PWR tWRDYL PRDY/SWAIT tARLDLY tARWDLY tWDS tWDH tWRH
Note:
The PRDY signal may be output depending on the internal state of the MSM9225B.
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Separate Bus/Address Latch Mode Read access timing
tHRC CS tWALEH PALE tAS tAH A7-0 don't care tHRA
tcyc
AD7-0/ D7-0
tRS
tRDLY tARDDLY
tRDH
tWRDH
PRD/SRW tWRDYL PRDY/SWAIT tARLDLY
Note:
The PRDY signal may be output depending on the internal state of the MSM9225B.
Write access timing
tHWC CS tWALEH PALE tAS tAH A7-0 don't care tHWA
tcyc
AD7-0/ D7-0 tWS PWR tWRL tWRDYL PRDY/SWAIT tARLDLY tARWDLY tWDS tWDH tWRH
Note:
The PRDY signal may be output depending on the internal state of the MSM9225B.
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Multiplexed Bus Mode Read access timing
tHRC CS tWALEH PALE tAS tAH AD7-0/ D7-0 tRS PRD/SRW tWRDYL PRDY/SWAIT tARLDLY tRDLY tARDDLY tRDH tWRDH tcyc tHRA
Note:
The PRDY signal may be output depending on the internal state of the MSM9225B.
Write access timing
tHWC CS tWALEH PALE tAS tAH AD7-0/ D7-0 tWS PWR tWRL tARWDLY tWDS tWDH tWRH tcyc tHWA
tWRDYL PRDY/SWAIT tARLDLY
Note:
The PRDY signal may be output depending on the internal state of the MSM9225B.
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Serial Mode Read access timing
CS tCS tCW tCW tDS SDI tDH tWAIT tCH
tCP
SCLK
A0
A1
A6
A7 tPD
Don't Care tCSZDLY
tCSODLY SDO tRS PRD/SRW tSRDLY PRDY/SWAIT tWRDY DMY0 DMY1 DMY6 DMY7 D0 tRH
Note:
The SWAIT signal will be output during the interval between address and data transfers.
Write access timing
CS tCS tCW tCW tDS SDI tDH tWAIT tCH
tCP
SCLK
A0
A1
A6
A7
D0 tCSZDLY
tCSODLY SDO tRS PRD/SRW tSRDLY PRDY/SWAIT tWRDY * * * * *
tRH
Note: The SWAIT signal will be output during the interval between address and data transfers. * : don't care
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Other Timing
tWRSTL RESET tWRSTH
tWINTL INT
tclkcy CLK (XT) tclkcy
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PACKAGE DIMENSIONS
(Unit: mm)
QFP44-P-910-0.80-2K
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 0.41 TYP. 4/Nov. 28, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-todate. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2001 Oki Electric Industry Co., Ltd.
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